EDN

BIST versus ATPG — separating myths from reality

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...
Electronic Design

Design for Test: ATPG keeps pace with design complexity

Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.
EDN

Designs with multiple clock domains: New tools avoid clock skew and reduce pattern counts

Nothing accelerates a testability engineer's receding hairline as the addition of further clock domains to the latest SoC or IC design. Avoiding clock skew during test is becoming one of the biggest ...
Electronic Design

Applying Advanced Fault Models

The current shift in the test methodologies is away from the ubiquitous single stuck-at fault model. The best test for any device is to exhaustively test the device. The quality of such a test would ...
Design-Reuse

BIST versus ATPG -- separating myths from reality

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...