Synopsys is broadening its DesignWare silicon and verification IP portfolio by announcing the availability of a lineup of SystemC transaction-level models called the DesignWare System-Level Library.

MOUNTAIN VIEW, Calif., Jan 12 /PRNewswire-FirstCall/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and ...

SAN JOSE, Calif.--(BUSINESS WIRE)--April 3, 2006--CoWare(R) Inc., the leading supplier of electronic system-level (ESL) design software and services, announced it has added new IP models to the CoWare ...

Transaction-level modeling – an abstracted representation of design IP above the RT level — continues to grow in importance for architectural exploration, performance analysis, building virtual ...

It has been proposed for some time that virtual platforms could be linked to emulation hardware in order to co-verify the software and hardware components of an SoC. However, that proposal now has ...